----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:13:33 03/24/2011 
-- Design Name: 
-- Module Name:    Flags - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.Definitions.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Flags is
    Port ( clk_i        	: in  STD_LOGIC;
           clr_i        	: in  STD_LOGIC;
           flags_in     	: in  STD_LOGIC_VECTOR (1 downto 0);
			  flags_alu 		: in  STD_LOGIC_VECTOR (1 downto 0);
           is_ret_state 	: in  STD_LOGIC;
			  reg_flag_enable : in STD_LOGIC;
           flags_out 		: out  STD_LOGIC_VECTOR (1 downto 0)
		    );
end Flags;

architecture Behavioral of Flags is

begin

Flags : process (clr_i, clk_i, is_ret_state, reg_flag_enable, flags_alu)
	begin
		if (reg_flag_enable = '1') then
			if(clr_i = '1') then
						flags_out <= (others => '0');
			else if rising_edge(clk_i) then
					if (is_ret_state='1')  then
								flags_out <= flags_in;
					else 
								flags_out <= flags_alu;
					end if;
				end if;
			end if;
		end if;
end process;


end Behavioral;

